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P4 or PM

post #1 of 21
Thread Starter 
I was wondering what was better/faster for a laptop processor. My friend and I are arguing that his Dell XPS P4 3.4 ghz processor is superior to my Asus z70v pentium M 2 ghz processor. I thought the 2 ghz pm was equivalent to a 3.6 p4 but I could be wrong and sorry to anyone who finds this as childish but this arguement needs to end. Thanks for the help!
post #2 of 21
i think they are probably about even. id choose the pM though because its cooler and stuff
post #3 of 21
Yep, I'd say P-M too. His might be a leeetle bit faster, but its not worth the extra heat and incredibly low battery life.
post #4 of 21
you guys are right on, the performance should be about dead even; with P4 having the advantage in things like encoding and content creation.
post #5 of 21
Quote:
Originally Posted by HardBall
you guys are right on, the performance should be about dead even; with P4 having the advantage in things like encoding and content creation.
Then the performance isn't dead on and the Pentium 4 is superior to the Pentium M (in this instance).
post #6 of 21
Well yes, technically it won't be dead even.
The P4 will be faster on streaming applications (encoding/transcoding) and the Pentium M will be faster in games. For most other applications the two will be so close as to not make a difference.

Depending on the particular mix of applications you tend to run, the end result is usually a wash.
post #7 of 21
Could someone explain to me why the Pentium M is faster in games?

What does that mean? Pound for pound, the pentium M is better at rendering graphics than a Pentium 4?
post #8 of 21
Quote:
Originally Posted by Studio54
Could someone explain to me why the Pentium M is faster in games?

What does that mean? Pound for pound, the pentium M is better at rendering graphics than a Pentium 4?
It's not rendering performance--that's the video GPU's job.
It has to do with the combination of a decent branch predictor and a much shorter pipeline in the Pentium M versus the good branch predictor and ridiculously-long pipeline in the Pentium 4.
Games (in particular Game AI) is branch based--that is, lots of "if A then B else C" branching, many many times--these are just what the Pentium 4 isn't the greatest at.

Branch mis-prediction penalties on the Pentium 4 are horrendous.

Also, (non-SSE) floating point performance is sub-par on the Pentium 4. The Pentium M's, on the other hand, is quite good.
post #9 of 21
Quote:
Originally Posted by Studio54
Then the performance isn't dead on and the Pentium 4 is superior to the Pentium M (in this instance).
Well, if you actually read my post carefully, that's exactly what I said: in most applications they are about the same, but in SIMD applications, P4 will have a significant edge.
post #10 of 21
Quote:
Originally Posted by HardBall
Well, if you actually read my post carefully, that's exactly what I said: in most applications they are about the same, but in SIMD applications, P4 will have a significant edge.


I don't think I'm speaking (or typing) in Swahili.

The man was asking which processor is superior. If they are both the same EXCEPT for SIMD applications at which the Pentium 4 trumps the Pentium M, then the Pentium 4 is SUPERIOR to the Pentium M(in this instance).

Edit: I feel a need to idiot proof it.

Basically, they are not equal because the Pentium 4 bests that Pentium M in SIMD applications.
post #11 of 21
Thread Starter 
Wow thanks for the response I appreciate it.
post #12 of 21
Quote:
Originally Posted by Studio54


I don't think I'm speaking (or typing) in Swahili.

The man was asking which processor is superior. If they are both the same EXCEPT for SIMD applications at which the Pentium 4 trumps the Pentium M, then the Pentium 4 is SUPERIOR to the Pentium M(in this instance).

Edit: I feel a need to idiot proof it.

Basically, they are not equal because the Pentium 4 bests that Pentium M in SIMD applications.
OK, agreed, we were just speaking with different mannerisms and flairs.

On the other hand, thorndt is right about all those shortcomings of the P4 that are holding it back, in terms of the length of the pipeline (31 stages, as opposed to the ~15 stages of the PM, and the 12 stages of A64); pipeline stalls created by BP miss; adding in the throttling problems on most of the prescott/smithfields, then you have a CPU that will never perform upto its potential.

But I have to say that the FP unit in the PM is not any better than that of the P4, since it's based on actually older technology of the P6 core from the mid-nineties. The problem with P4's FP units, is that not all of them are able to perform every type of operation; it has 2 double clocked ALUs, one complex IEU, and two FP/SIMD units. This compares to 3 ALUs and 3 FP/SIMD units in A64; that's why the P4 is more integer heavy, since in real operation it has twice the interger execution capacity as FP;and with the inefficiencies in the architecture, the ALUs can cope quite well, since there is a quite bit of excess for performance; but the FPs are really affected by these pipeline inefficiencies, comparred to that of the rival architecture.

CPU does play a secondary role in graphics and rendering, since it calculates the initial vertex data and stores this information in the region of the system memory that is termed "geometry buffer" or "vertex buffer", then the manipulations of these vertices begins in the vertex pipelines.
post #13 of 21
No problemo. Glad to be of service.
post #14 of 21
Well, the thing is: a key design decision for the P4 is that they simplified the floating point unit in the Pentium 4.

Excerpt:

Quote:
* A relatively simple FPU — The Pentium 4's floating-point unit isn't as capable as the FPU in the Pentium III, and it's quite a bit less capable than the Athlon's hoss FPU. To put it simply, the P4's FPU can't do as much work at once, and it has higher latencies in some cases. Programs optimized for SSE2 will be able to bypass the P4's FPU in many cases, but without special optimizations, the P4 will have a hard time keeping up.

Intel's decision to include a relatively weak FPU in the P4 is perplexing. Based on comments by Intel engineers after the fact, it appears they may have been forced to scale back their original FPU plans to keep within their transistor budget. It's possible a future revision of NetBurst might include a more robust floating-point unit, once a die shrink makes it practical.
This from http://techreport.com/reviews/2001q1/pentium4/
post #15 of 21
Quote:
Originally Posted by galahad05
Well, the thing is: a key design decision for the P4 is that they simplified the floating point unit in the Pentium 4.

Excerpt:



This from http://techreport.com/reviews/2001q1/pentium4/
You are quoting from an article dated to Q1 of 2001, which was likely talking about the the original P4 Willamette core, built on 180 nm process; that was nearly 4 1/2 years ago, long before the introduction of the A64, PM or even Athlon XP!!

There has been two major revisions of the netburst cores since that time, and each saw a substantial improvement of the FP performance.

First the Northwood core revision with 130nm process, for example:
http://www.vr-zone.com/reviews/Intel...wood/page2.htm

Quote:
Originally Posted by vr-zone
Hyper-pipelined technology, Rapid execution engine, Execution trace cache, Advanced transfer cache, Advanced dynamic execution, Enhanced floating point/multimedia and
Streaming SIMD extensions 2 (SSE2).
And the prescott 90nm revision:
http://www.digit-life.com/articles2/...-prescott.html

Quote:
Originally Posted by digit-life
Besides, there's a number of smaller improvements to speed up the FPU (and MMX) processing. But we better test it further in the article, in the test part.
Although the second revision turned out to be less successful than the first NW one, especially in that the new inefficiencies brought about by the 31 stages pipeline had large negative impact on the branch target table and on the improvements that they were attempting to achieve for the FP calculations -- what improvements they achieved were negated largely by the new detractions:

Quote:
Originally Posted by digit-life
It's absolutely identical. If you compare it with the previous, you will see that our thoroughness justifies itself: if we considered only the best (dual-thread) result, we would make a wrong conclusion that Prescott is faster in the instruction processing even with MMX/FPU. Now we can clearly see that the performance grew only due to optimized usage of virtual CPU resources.
But the prescott was only the third of four or more major versions of netburst planned by intel, only a temporary solution, a testing bed from 90nm, LGA775, and some of the newer technologies such as EIST and SSE3. But as we know now, what would be the fourth version of P4, Tejas, never came, so prescott and prescott derivatives (smithfield, presler) have to hold the tent until conroe arrives in late 06:

Just read the sentiment at the time when prescott was first released:
Quote:
It's not a secret that sometimes a manufacturer needs to release a solution that's rather ordinary itself (and in another situation unimportant), but still required to help advance other solutions announced alongside or afterwards. Such a solution was Pentium 4 Willamette hardly good and fast, but designating the fact of transition to the new core. At the end of its life cycle it replaced the "intermediate" Socket 423 with a long-term Socket 478. What if Prescott is intended for the same role?

As you all know, alongside Grantsdale-P we should see another Pentium 4 socket (Socket T / Socket 775 / LGA775) that will initially be used for Prescott CPUs exactly. And only after time passes Pentium 4 "Tejas" will be replacing them gradually. Here it would be logical to ask how fast would this "gradually" mean? As we are only putting versions forward, let's not limit our fantasy and assume that Intel wishes to speed up this process as much as possible. But how? Most likely, leaving the bottom places in performance ratings to Socket 478 and making Socket 775 a symbol of an improved, powerful Pentium 4 platform. This makes everything clear: Prescott is required so in the market there's a processor capable of working in both Socket 478, and Socket 775 motherboards. And the Tejas, given we are correct, is to be installed into Socket 775 only undertaking both Prescott and Socket 478. Logical, isn't it? We guess it is. In this case, Prescott shouldn't live for long...

SO what you were talking about was basically a CPU core that is two generations and nearly 5 years back in time; and the situation of the FPU in today's P4s are vastly different.
post #16 of 21
Hey, thanks for the good info Hardball.
post #17 of 21
Quote:
Originally Posted by galahad05
Hey, thanks for the good info Hardball.
Thank YOU, for listening me ramble on.

It's always good to have an intelligent conversation with someone.
post #18 of 21
Okay, I took a look at the articles...just skimmed them really.
Am I right in that the articles point to major step ups in SIMD performance (SSE2 and now SSE3) while the "regular" FP stuff is just a tweaked version of the original? It wasn't clear to me...

EDIT: Or, perhaps, there were major upgrades to even the regular FP functions but were counterbalanced by the penalties inherent to the longer 31-stage pipeline? So, in the end, SIMD was a major boost, but regulard FP operations were just a little better?
post #19 of 21
Quote:
Originally Posted by galahad05
Okay, I took a look at the articles...just skimmed them really.
Am I right in that the articles point to major step ups in SIMD performance (SSE2 and now SSE3) while the "regular" FP stuff is just a tweaked version of the original? It wasn't clear to me...

EDIT: Or, perhaps, there were major upgrades to even the regular FP functions but were counterbalanced by the penalties inherent to the longer 31-stage pipeline? So, in the end, SIMD was a major boost, but regulard FP operations were just a little better?
The details of each redesign were a closely guarded secrete, and there are much speculation, plus some useful information about each, such as this one, which comes from some detailed analysis from intel die photos:
http://www.geek.com/news/geeknews/20...0307019009.htm
http://www.chip-architect.com/news/2..._Prescott.html

Quote:
Originally Posted by chip-architect.com
The top two images below are from one of the Intel presentation sheets. They show what the lay-outer sees on his monitor when looking at the Floating Point units of Northwood and Prescott. The Prescott view shows how various units are intertwined. This because the layout software was allowed to place cells anywhere it wants in the entire area unlike Northwood's case where it wasn't allowed to place cells outside their own bounding box.

The two middle images show the same Floating Point units. The Northwood version comes from a high resolution die plot while the vague Prescott Floating Point unit was found on Prescott die plot shown during the spring 2003 IDF.

The lower two images show how the location has changed. Again this shows that Prescott is a significant change from its Willamette / Northwood predecessors
post #20 of 21
Thanks again for the new info, Hardball.

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