New Posts  All Forums:Forum Nav:

Howto: D900T + P4 6x0 + EIST + Linux

post #1 of 12
Thread Starter 
I just got done hacking the DSDT/SSDT Tables of this bios to have it advertise the EIST speeds for my p4-630 I added. I could find NO references on how to do this anywhere, so I wrote up a short howto.

If Any of what I have written there scares you, stop here.

http://pat.erley.org/Other/P4EISTSSDT

What have I accomplished with all of this work?

* I understand ACPI/DSDT/SSDT much better now
* I can on the fly switch from 2.8 to 3ghz and back.
post #2 of 12
Impressive project Thanks for sharing.

cheers ...
post #3 of 12
Thread Starter 
Quote:
Originally Posted by qhn View Post
Impressive project Thanks for sharing.

cheers ...
Thanks, just updated. Fixed HT CPU EIST. now both 'CPUs' change together... it WAS only working whenever the latest CPU was changed into the desired state... IE, we want LOW Volt Usage, we set one or the other to 2.8Ghz, if they're both in Low, and it set ONE high for medium, both went high. Adding a PSD entry fixed that.
post #4 of 12
That's quite some work. How did you go about deciding what (entry) to add? Trial and error?

cheers ...
post #5 of 12
Thread Starter 
Quote:
Originally Posted by qhn View Post
That's quite some work. How did you go about deciding what (entry) to add? Trial and error?

cheers ...
Scarily....


Reading the ACPI 4.0 Specs

I nearly had an aneurysm or two... It's almost as boring as reading the 802.11 Specs were while I was doing some wifi development.
post #6 of 12
That was scary indeed. Specifications reading is never my forte Glad that my programming days are practically over

cheers ...
post #7 of 12
Holy crap-That was impressive s0be.
post #8 of 12
Thread Starter 
Updated to include functional C1/C2... the ICH6/ICH6-R chipset doesn't support anything beyond C2, so all that is left is C1E (which might 'just work' with C1, still researching).

So here's what I've accomplished so far(in order)

* Cleaned up DSDT
* Added P-States & enabled EIST
* Added PSD entries to get HT CPUs to switch together
* Added C-States C1 & C2

My system is now MUUUUUCH cooler.
post #9 of 12
Interesting. Keep up the good work, and thanks for informing us of your progress.
post #10 of 12
Thread Starter 
Quote:
Originally Posted by s0be View Post
Updated to include functional C1/C2... the ICH6/ICH6-R chipset doesn't support anything beyond C2, so all that is left is C1E (which might 'just work' with C1, still researching). So here's what I've accomplished so far(in order) * Cleaned up DSDT * Added P-States & enabled EIST * Added PSD entries to get HT CPUs to switch together * Added C-States C1 & C2 My system is now MUUUUUCH cooler.
I now have C1E working. This can be noted from the cpuidle line from dmesg:
Code:
using mwait in idle threads.
a kernel update enabled it, so it looks like it not working was a bug. I also enabled C3 and C4, all working, disabled HT (hyperthreading was causing more harm than good, in my case). I originally left out C3 and C4 because they were listed as 'mobile only' which I thought meant ICH6-M, but it turns out, they work fine on any supported CPU, just that they should 'probably' only be enabled on a mobile CPU. here's some more interesting output:
Code:
boatanchor ~ $ for f in /sys/devices/system/cpu/cpu0/cpuidle/*/*; do echo $f: `cat $f`; done;
/sys/devices/system/cpu/cpu0/cpuidle/state0/desc: CPUIDLE CORE POLL IDLE
/sys/devices/system/cpu/cpu0/cpuidle/state0/latency: 0
/sys/devices/system/cpu/cpu0/cpuidle/state0/name: C0
/sys/devices/system/cpu/cpu0/cpuidle/state0/power: 4294967295
/sys/devices/system/cpu/cpu0/cpuidle/state0/time: 0
/sys/devices/system/cpu/cpu0/cpuidle/state0/usage: 0
/sys/devices/system/cpu/cpu0/cpuidle/state1/desc: ACPI HLT
/sys/devices/system/cpu/cpu0/cpuidle/state1/latency: 1
/sys/devices/system/cpu/cpu0/cpuidle/state1/name: C1
/sys/devices/system/cpu/cpu0/cpuidle/state1/power: 1000
/sys/devices/system/cpu/cpu0/cpuidle/state1/time: 2703
/sys/devices/system/cpu/cpu0/cpuidle/state1/usage: 3
/sys/devices/system/cpu/cpu0/cpuidle/state2/desc: ACPI IOPORT 0x1014
/sys/devices/system/cpu/cpu0/cpuidle/state2/latency: 1
/sys/devices/system/cpu/cpu0/cpuidle/state2/name: C2
/sys/devices/system/cpu/cpu0/cpuidle/state2/power: 500
/sys/devices/system/cpu/cpu0/cpuidle/state2/time: 8847685140
/sys/devices/system/cpu/cpu0/cpuidle/state2/usage: 15304006
/sys/devices/system/cpu/cpu0/cpuidle/state3/desc: ACPI IOPORT 0x1015
/sys/devices/system/cpu/cpu0/cpuidle/state3/latency: 85
/sys/devices/system/cpu/cpu0/cpuidle/state3/name: C3
/sys/devices/system/cpu/cpu0/cpuidle/state3/power: 250
/sys/devices/system/cpu/cpu0/cpuidle/state3/time: 42073229
/sys/devices/system/cpu/cpu0/cpuidle/state3/usage: 4674565
/sys/devices/system/cpu/cpu0/cpuidle/state4/desc: ACPI IOPORT 0x1016
/sys/devices/system/cpu/cpu0/cpuidle/state4/latency: 150
/sys/devices/system/cpu/cpu0/cpuidle/state4/name: C4
/sys/devices/system/cpu/cpu0/cpuidle/state4/power: 100
/sys/devices/system/cpu/cpu0/cpuidle/state4/time: 625543763
/sys/devices/system/cpu/cpu0/cpuidle/state4/usage: 69504596
Code:
boatanchor ~ $ cat /proc/acpi/processor/CPU0/power
active state:            C0
max_cstate:              C8
maximum allowed latency: 2000000000 usec
states:
    C1:                  type[C1] promotion[--] demotion[--] latency[001] usage[00000003] duration[00000000000000000000]
    C2:                  type[C2] promotion[--] demotion[--] latency[001] usage[15365785] duration[00000000031792551914]
    C3:                  type[C3] promotion[--] demotion[--] latency[085] usage[04688892] duration[00000000000150050985]
    C4:                  type[C3] promotion[--] demotion[--] latency[150] usage[69723517] duration[00000000002231159790]
Code:
@boatanchor ~ $ for f in /proc/acpi/thermal_zone/THM0/*; do echo $f\\: `cat $f`; done;
/proc/acpi/thermal_zone/THM0/cooling_mode: 0 - Active; 1 - Passive
/proc/acpi/thermal_zone/THM0/polling_frequency: <polling disabled>
/proc/acpi/thermal_zone/THM0/state: state: ok
/proc/acpi/thermal_zone/THM0/temperature: temperature: 48 C
/proc/acpi/thermal_zone/THM0/trip_points: critical (S5): 85 C passive (forced):<not set>
The only missing feature is TM2... which I have no clues on howto go forward on.
post #11 of 12
What a nice job, well done
However I´ve to ask ¿doesn´t have the BIOS version 1.12 support for this processor?
post #12 of 12
Thread Starter 
Quote:
Originally Posted by Alien_Mecha View Post
What a nice job, well done
However I´ve to ask ¿doesn´t have the BIOS version 1.12 support for this processor?
Only rudimentary support. It only enables the CPU and makes it work, not actually supporting the features like P-States, C-States, C1E/Mwait, or TM2. I have all but TM2 working.

The results:

Default: idle: 62C loaded: 67C
DSDT Patched: idle: room temp (30C or so) loaded: 57C
New Posts  All Forums:Forum Nav:
  Return Home