C1E in P4 CPUs

I have an alienware 7700 (old) notebook that I've upgraded to a P4 630. The new CPU supports things like C1E halt states, and EIST. Unfortunately, the Bios never supported such features. I've modified my SSDT and DSDT tables to support EIST and P-States, but have hit a brick wall on the C-States.

Does anyone have a system that has a P4 6xx series cpu in it, and working C1E enhanced wait? If so, could someone dump their DSDT and SSDT tables, and e-mail them to me? I think I've figured out how to add the C1 state, but not C1E.

You can find details about my DSDT/SSDT hacks at: http://pat.erley.org/Other/P4EISTSSDT

I learned 80% of this from the ACPI-4.0 spec, and 20% from google.

It's not that I need a full ACPI implementation that's out of the ordinary.... I literally just need a DSDT dump from a P4 System that supports C1E (enhanced sleep). But I believe the point to be moot now. I've moved onto a bigger project:

http://pat.erley.org/Other/D900TCoreboot

It's cool to have someone say that I outrank others on this board in something, although I'm 100% certain that there's someone else on the board that knows more about Bioses and/or ACPI/DSDT stuff than I do. I did, however, kick my geekiness up to a new level with these projects.

Oh yeah it'll be a lot of work... there's no ICH6 support yet, not i915P support yet, no Socket 775 support(trivial), I've been unable to find out my EC chip definitively, there is no KBC in the super-i/o.... should only take me 6-7 months to be ready to attempt a flash that might make my laptop true to it's name (boatanchor)

How dual bios can work:

There are multiple address pins on these chips. Generally, a dual bios works one of a couple ways. The easiest to implement, but the toughest on 'Users' is dual bioses with a chip enable toggle (this is what I'm going to do). The general way most people seem to do it is a second flash chip that is addressed onto the end of the first (first flash is 0M-2M, second flash is 2M-4M), and some magic code in the beginning of the first flash (that doesnt' get overwritten) that detects when the bios doesn't finish loading, and hands off to the second flash chip.

An alternative fallback is, during that same bootstrap code (the beginning of the bios), there's a magic key you press during power on that causes the bootstrap to load the floppy and autorun it (but at a much earlier level, before PCI/AGP are enabled, stuff like that) to recover from a bad flash. I had to do this on a K6-II mobo around 2001 once... it's hairraising to watch your computer flash itself with NO display output

My Plan

First, the D900T motherboard has 2 spots for flash chips, but only one populated. This board was designed to be dual bios, in some manner. For coreboot development, you (basically) MUST have dual bios, or a removable bios. The D900T bios chip is a PLCC32 non socketed chip. I'm going to solder a PLCC32 socket onto the spot for the second flash chip, cut the Chip Enable trace to the original bios, and install a switch to allow me to toggle which flash gets the CE signal. Of course, first I'm going to verify the address traces and whatnot to verify this can work. If not, I'm going to solder the socket directly ONTO the current bios chip, with a CE switch. Due to teh location of the flash chip, this approach will require a case-mod to allow the keyboard to populate roughly the same location.

The switch will be labeled: Magic / More Magic

Nope, you were correct, as far as I understand... I just enjoy hardware hacking. Most people are using PLCC Sockets with thumbtacks glued to the top of their bios chips. this is just REALLY inconvenient inside a laptop. There's also a product called Bios Savior that people commonly use.