Dell has offering new CPU for Alienware
all the x20 modles becomes X40 family:
740QM
840QM
940XM
Like other Core i7 Mobile models, the 740QM utilizes two different interfaces to access memory and peripheral devices. Instead of Front Side Bus interface, that was used in older processors for communications between the motherboard and the CPU, the i7-740QM uses integrated memory controller for memory accesses, and Direct Media Interface to talk to other devices. Integrated memory controller can work with two DD3 memory channels, which doubles its available bandwidth and increases CPU performance to some extent. Both the memory controller and Direct Media interface are located on the same die as four CPU cores. The die also contains 6 MB level 3 cache, which is 2 MB less than L3 cache on more powerful i7-8xx line of mobile microprocessors. Each CPU core has its own level 1 (L1) and level 2 (L2) caches, and those are used to store only the data used by the core. Level 3 cache, on the other side, is shared between all cores, and stores data for all of them. Even more, the L3 cache is inclusive, i.e. it also stores data located in each core's L1 and L2 caches. This make it easier for any core to find previously cached data, even if it was cached by another core. The disadvantage of this method is in reduced effective size of the L3 cache, as some cache data is duplicated in L1/L2 and L3 caches.
all the x20 modles becomes X40 family:
740QM
840QM
940XM
Like other Core i7 Mobile models, the 740QM utilizes two different interfaces to access memory and peripheral devices. Instead of Front Side Bus interface, that was used in older processors for communications between the motherboard and the CPU, the i7-740QM uses integrated memory controller for memory accesses, and Direct Media Interface to talk to other devices. Integrated memory controller can work with two DD3 memory channels, which doubles its available bandwidth and increases CPU performance to some extent. Both the memory controller and Direct Media interface are located on the same die as four CPU cores. The die also contains 6 MB level 3 cache, which is 2 MB less than L3 cache on more powerful i7-8xx line of mobile microprocessors. Each CPU core has its own level 1 (L1) and level 2 (L2) caches, and those are used to store only the data used by the core. Level 3 cache, on the other side, is shared between all cores, and stores data for all of them. Even more, the L3 cache is inclusive, i.e. it also stores data located in each core's L1 and L2 caches. This make it easier for any core to find previously cached data, even if it was cached by another core. The disadvantage of this method is in reduced effective size of the L3 cache, as some cache data is duplicated in L1/L2 and L3 caches.
