Further Proof that the 9800 Mobility is based on X800 tech

hmmm I just finished reading some info on beyond3d.com ( a site someone gave me a while back and i just now decided to read it )

And it too was talking about the chip being R420 and they thought the pipes were disable for the fact to make 2 differ cards with one chip and heat....

Im excited to read this... I want some more pipes... They were talking the 4 pipes opened added a boat load of performance.... very excited! cant wait to get these pipes opened........

Same here. Sounds awesome getting more bang for the buck and all. ATI should have just opened all pipelines, they would have made their cards leaps and bounds faster than the nVidia at the time. You know how they're always neck and neck (ATI is always better IMO...even if nVidia clearly shows higher performance :P).

the question is where is whack? we want whack, -a-mac

A dude on this forum with an alienware got like around 8300 or higher on his 6800 on the 3dmark03 program. i wonder what a 9800 mobility unlocked would get !!! come on whack!

If whackamac unlocks it, im getting it!

Come on, the future of m18 is in your hand!

i've gotten around 8700 stable on the M18 that i have with just some AS5.

http://www.geocities.com/mnguyen281/score.jpg

your mtexel count is doubled compared to mine. Impressive.

anyone have any idea what happened to wac, i havent seen any posts from him in a long time...

Core/Mem speeds?

i don't think there's much he can do without the MRX800 bios. i remember him saying that he needed it to see how the video ports were coded. i've been asking him which tools he uses to edit the bios but have gotten no replies.

luckily i've found a guy on the sager forums that should be getting is HS ex7 soon w/ the x800 and he said he'd be willing to dump the bios of me.

ya i read your other thread hulk about the bios, my question is, why isnt wac all over this. It's like he has just disappeared... with the release of a couple laptops with the x800 I just don't see where he has gone. The thought of 4 or even 8 more pipelines... I hope he comes back

i'm sure he's got a job and a family that most likely take precedence over hacking a video card for a bunch of drooling geeks like us. lol

hmmm, a life more important the video games and geeks, naw...

News Update. Three 220 pound "dell representatives" showed up at Whack's colonial home at 1:25pm to discuess his quest for unlocking a reported 4 additional pipes from the mobility radeon 9800. Nearby neighbors saw the three men lift Whack off the ground and place him in a new model SUV where he was transferred to Jackson State Prison for an undisclosed amount of time.

lol, how do u respond to that...

here's the log from using rabit 1.5 in editting the 9800 bios. note this line:

"Radeon family: Radeon X800 series" there's your proof that the mr9800 is an x800


-- RaBiT v.1.5.0 build 320 --
> RaBiT driver v.1.0.5 is loaded
Readed from file: 66560 bytes, ROM len: 66560 bytes
-- Analyze ROM BIOS --
> HEADER offs: 0x118
> PCIR struct offs: 0x184
> CRC table offs: 0x1BA
> CLOCK table offs: 0x136A
Core clock is 350.00 MHz
Memory clock is 299.25 MHz
Reference clock is 27.00 MHz
> DRAM table offs: 0x208
MEM info: MC_CNTL(0x00000062), memory size = 256 Mb
> Memory config: 0x6280
> TV table offs: 0xF0B
Active TV type: 'NTSC'
> DFP table offs: 0xE32
DFP table Ver.4, 2 preset(s)
TMDS_PLL(1FBB011C), freq = 150.00 MHz
TMDS_PLL(1FBB011C), freq = 200.00 MHz
> Connectors Layout table offs: 0xE2A
Conn0 type = DVI-I, DDC = DVI, DAC = Primary
Conn1 type = VGA, DDC = VGA, DAC = Unknown
ASIC init: 0x75 = 0x00, 0x74 = 0x12
ASIC init: 0x7B = 0x03, 0x7A = 0x40 (0x00000340)
-- ROM BIOS info --
Desc: ATI 9800 BIOS PN#113-A25204-103
Info: M18AGP DDRUN, njdell9.711 v611 , 2004/10/13 13:45
Radeon family: Radeon X800 series
-- Parsing hardware scripts: --
> PLL script at 0x08B1
> INIT script at 0x0233
> MEMORY script at 0x0738
-- Found hardware registers values: --
> MC_TIMING_CNTL(0x65668344) at 0x072B
> MC_CNTL(0x00000062) at 0x06E9
> MC_SDRAM_MODE_REG(0x10230000) at 0x0731
> MC_CHP_IO_OE_CNTL_CD(0x4FF04FF0) at 0x0725
> MC_READ_CNTL_CD(0x0A4A0A4A) at 0x0303
> MC_READ_CNTL_AB(0x0A4A0A4A) at 0x02F7
> MC_REFRESH_CNTL(0x00004830) at 0x02F1
> MC_CHP_IO_OE_CNTL_AB(0x4FF04FF0) at 0x0719
-- In BIOS memory timings --
tWL = 1.5
tCL = Reserved
tCMD = 0 clock
tSTB = equals tWrL
tRcdRD = 7
tRcdWR = 5
tRP = 6
tRAS = 6
tRRD = 6
tR2W = CL + 2
tWR = 7
tW2R = 5
tW2Rsb = Use tW2R Rule
tR2R = 3
MemRR = 30
tRFC = 17
tRBS = CL + 2
tERST = CL + 0
tQSREQ = CL - 1
tDQM = WL - 1
tDQS = WL - 1
tDQM_Adv = 1 clock earlier for WL 1 clock and more
tDQS_Adv = 1 clock earlier for WL 1 clock and more
-- Additional hardware SDRAM info --
SDRAM specific: 2**12 rows, 512 columns
SDRAM dynamic CKE is Enabled
! No M_SPLL_REF_FB_DIV found, Clocks settings is blocked
-- User changes followed --

What does it say with the latest version of RaBiT?
RaBiT v1.7

-- RaBiT v.1.7.2 build 390 --
> RaBiT driver v.1.0.5 is loaded
Readed from file: 66560 bytes, ROM len: 66560 bytes
-- Analyze ROM BIOS --
> HEADER offs: 0x118
> PCIR struct offs: 0x184
> CRC table offs: 0x1BA
> CLOCK table offs: 0x136A
Core clock is 350.00 MHz
Memory clock is 299.25 MHz
Reference clock is 27.00 MHz
> DRAM table offs: 0x208
MEM info: MC_CNTL(0x00000062), memory size = 256 Mb
> Memory config: 0x6280
> TV table offs: 0xF0B
Active TV type: 'NTSC'
> Hardware table: at 0xE20, Rev.2
hw_a: 0x000F, hw_b: 0x0002
> DFP table offs: 0xE32
DFP table Ver.4, 2 preset(s)
TMDS_PLL(1FBB011C), freq = 150.00 MHz
TMDS_PLL(1FBB011C), freq = 200.00 MHz
> Connectors Layout table offs: 0xE2A
Conn0 type = DVI-I, DDC = DVI, DAC = Primary
Conn1 type = VGA, DDC = VGA, DAC = Unknown
> VESA BIOS Extension 2.00, Rev. 1.00 info:
Vendor: ATI Technologies Inc.
Product: M18, Rev. 01.00
OEM: ATI MOBILITY RADEON 9800(M18)
> ASIC Config:
0x75 = 0x00, 0x74 = 0x12
0x7B = 0x03, 0x7A = 0x40 (0x00000340)
-- ROM BIOS info --
Desc: ATI 9800 BIOS PN#113-A25204-103
Info: M18AGP DDRUN, njdell9.711 v611 , 2004/10/13 13:45
Radeon family: Radeon X800 series
-- Parsing hardware scripts: --
> PLL script at 0x08B1
> INIT script at 0x0233
> MEMORY script at 0x0738
-- Found hardware registers values: --
> MC_TIMING_CNTL(0x65668344) at 0x072B
> MC_CNTL(0x00000062) at 0x06E9
> MC_SDRAM_MODE_REG(0x10230000) at 0x0731
> MC_CHP_IO_OE_CNTL_CD(0x4FF04FF0) at 0x0725
> MC_READ_CNTL_CD(0x0A4A0A4A) at 0x0303
> MC_READ_CNTL_AB(0x0A4A0A4A) at 0x02F7
> MC_REFRESH_CNTL(0x00004830) at 0x02F1
> MC_CHP_IO_OE_CNTL_AB(0x4FF04FF0) at 0x0719
-- In BIOS memory timings --
tWL = 1.5
tCL = Reserved
tCMD = 0 clock
tSTB = equals tWrL
tRcdRD = 7
tRcdWR = 5
tRP = 6
tRAS = 6
tRRD = 6
tR2W = CL + 2
tWR = 7
tW2R = 5
tW2Rsb = Use tW2R Rule
tR2R = 3
MemRR = 30
tRFC = 17
tRBS = CL + 2
tERST = CL + 0
tQSREQ = CL - 1
tDQM = WL - 1
tDQS = WL - 1
tDQM_Adv = 1 clock earlier for WL 1 clock and more
tDQS_Adv = 1 clock earlier for WL 1 clock and more
-- Additional hardware info --
SDRAM specific: 2**12 rows, 512 columns
SDRAM dynamic CKE is Enabled
! No M_SPLL_REF_FB_DIV found, Clocks settings is blocked
-- User changes followed --