I HAVE THE MX800 BIOS!!!!! Thanks Syn! - Page 4

i haven't had time to really give rivatuner a test drive, but i'm hoping they have source code on that russian site. that way we might be able to reverse engineer their hardware unmasking algorithm.

UPDATE from Atitool

i just downloaded the 0.24 beta. when holding shift and clicking on settings, you get some additional parameters in the overclocking "tab"

CONFIG_DIE_FUSES
CONFIG_SUBSTRATE_FUSES
CONFIG_ROM_FUSES
GB_PIPE_SELECT

variable, you sent this info the w1zzard the other day. can you or anyone else post those values here?

let's start with the m9800. but obviously both would be better. since they're hex values, we can look in the bios and see where they lie. we can then compare it with the x800 homolog and see if there are significant differences.

if we had the x800 values also, then we can make a statement about the overall structures of the bioses. if the predicted homolog from the 9800 bios is actually present in the x800 then the bioses are similar and using 1 as a guide would be relevant. but if the x800 homolog is found in a completely different area of the bios, then maybe we should just focus on the 9800 bios.

just speaking as a computational geneticist here...

interesting indeed. obviously the GB_PIPE_SELECT value seems the most interesting but since the CONFIG_DIE_FUSES value also varies, lets see if there's a correlation between these 2 values.

**** OK GENERAL CALL FOR HELP ****
everyone post your values from atitool 0.24 beta. i know it's like looking for a needle in a haystack, but variations seem to be the best place to start.

i've sent an email to synergi asking for her to give us values from the mx800 as well.

in comparing the rabit 1.7 logs of both bioses, here's what we get:

here's how to read this log:

#,#c#,# - refers to line line x in the first file and line y in the second file
< - refers to the entry in the first file
> - refers to the entry in the second file

3c3
< Readed from file: 66560 bytes, ROM len: 66560 bytes
---
> Readed from file: 65536 bytes, ROM len: 65536 bytes
5,10c5,10
< > HEADER offs: 0x118
< > PCIR struct offs: 0x184
< > CRC table offs: 0x1BA
< > CLOCK table offs: 0x136A
< Core clock is 350.00 MHz
< Memory clock is 299.25 MHz
---
> > HEADER offs: 0x112
> > PCIR struct offs: 0x180
> > CRC table offs: 0x1B9
> > CLOCK table offs: 0x148C
> Core clock is 398.25 MHz
> Memory clock is 351.00 MHz
12c12
< > DRAM table offs: 0x208
---
> > DRAM table offs: 0x207
15c15
< > TV table offs: 0xF0B
---
> > TV table offs: 0xC91D
17,19c17,19
< > Hardware table: at 0xE20, Rev.2
< hw_a: 0x000F, hw_b: 0x0002
< > DFP table offs: 0xE32
---
> > Hardware table: at 0xF2D, Rev.2
> hw_a: 0x330F, hw_b: 0x0000
> > DFP table offs: 0xF3D
23,25c23,25
< > Connectors Layout table offs: 0xE2A
< Conn0 type = DVI-I, DDC = DVI, DAC = Primary
< Conn1 type = VGA, DDC = VGA, DAC = Unknown
---
> > Connectors Layout table offs: 0xF37
> Conn0 type = DVI-I, DDC = VGA, DAC = Unknown
> Conn2 type = VGA, DDC = DVI, DAC = Unknown
28,29c28,29
< Product: M18, Rev. 01.00
< OEM: ATI MOBILITY RADEON 9800(M18)
---
> Product: M28, Rev. 01.00
> OEM: ATI MOBILITY RADEON X800(M28) XT
31,32c31,32
< 0x75 = 0x00, 0x74 = 0x12
< 0x7B = 0x03, 0x7A = 0x40 (0x00000340)
---
> 0x75 = 0x44, 0x74 = 0x00
> 0x7B = 0x00, 0x7A = 0x40 (0x00000040)
34,35c34,35
< Desc: ATI 9800 BIOS PN#113-A25204-103
< Info: M18AGP DDRUN, njdell9.711 v611 , 2004/10/13 13:45
---
> Desc: M28 12P board 400m/400e
> Info: M28PCIEDDR3UN, jucld910.ts1 v611 , 2004/12/16 19:48
38,40c38,40
< > PLL script at 0x08B1
< > INIT script at 0x0233
< > MEMORY script at 0x0738
---
> > PLL script at 0x0952
> > INIT script at 0x0232
> > MEMORY script at 0x07D9
42,49c42,49
< > MC_TIMING_CNTL(0x65668344) at 0x072B
< > MC_CNTL(0x00000062) at 0x06E9
< > MC_SDRAM_MODE_REG(0x10230000) at 0x0731
< > MC_CHP_IO_OE_CNTL_CD(0x4FF04FF0) at 0x0725
< > MC_READ_CNTL_CD(0x0A4A0A4A) at 0x0303
< > MC_READ_CNTL_AB(0x0A4A0A4A) at 0x02F7
< > MC_REFRESH_CNTL(0x00004830) at 0x02F1
< > MC_CHP_IO_OE_CNTL_AB(0x4FF04FF0) at 0x0719
---
> > MC_TIMING_CNTL(0x69668234) at 0x07CC
> > MC_CNTL(0x00000062) at 0x078A
> > MC_SDRAM_MODE_REG(0x10430000) at 0x07D2
> > MC_CHP_IO_OE_CNTL_CD(0x5FC05FC0) at 0x07C6
> > MC_READ_CNTL_CD(0x082A082A) at 0x039E
> > MC_READ_CNTL_AB(0x082A082A) at 0x0392
> > MC_REFRESH_CNTL(0x0000882A) at 0x038C
> > MC_CHP_IO_OE_CNTL_AB(0x5FC05FC0) at 0x07BA
56,57c56,57
< tRcdWR = 5
< tRP = 6
---
> tRcdWR = 4
> tRP = 5
62,63c62,63
< tW2R = 5
< tW2Rsb = Use tW2R Rule
---
> tW2R = 1
> tW2Rsb = Use tWR Rule
65,66c65,66
< MemRR = 30
< tRFC = 17
---
> MemRR = 2A
> tRFC = 21
68,69c68,69
< tERST = CL + 0
< tQSREQ = CL - 1
---
> tERST = CL - 1
> tQSREQ = CL - 2